A panel for semiconductor components includes a composite plate with a plurality of semiconductor component positions, and the panel can be separated into a plurality of semiconductor components after completion of the panel. A panel of this type includes large-area plastic housing compositions. During the injection of plastic housing compositions of this type, or during the application of plastic housing compositions for protection of semiconductor chips and/or connecting elements arranged thereon (e.g., circuit substrates populated with semiconductor chips), the plastic housing composition is applied to the circuit substrate on one side with formation of a panel. When the plastic housing composition solidifies, it shrinks to a greater extent than the shaping substrate, which was not preheated, so that warping can occur due to the thermally dictated stresses that occur.
Such warping and deformations of a panel based on a circuit substrate for semiconductor components may be so great that the panel becomes unsuitable for further processing to form semiconductor components, particularly if it exceeds a delimited degree of deformation and has to be sorted out or rejected. In order to minimize the warping after the application of the plastic housing composition to the substrate, substrates are used which have an extreme stiffness and provide a planar intermediate product with applied plastic housing composition for the subsequent method steps.
German Patent Document No. DE 102 13 296 A1 discloses an electronic semiconductor component based on a panel with a circuit substrate, where the extreme stiffness of the wiring substrate is ensured by complying with the condition for the plastic of the circuit substrate that its glass transition temperature is significantly lower than the glass transition temperature of the plastic housing composition. This ensures that the substrate is already dimensionally stable when the plastic housing composition solidifies.
One disadvantage of this combination of extremely rigid circuit substrate and plastic housing composition (which is applied by injection-molding methods) is the high material outlay since the substrate has to have a minimum thickness in order to take up the thermal stresses with a minimum permissible warping. Moreover, there is constantly the risk of delamination between plastic housing composition and substrate for a panel constructed on a rigid substrate.
The problems become even greater for a panel produced in semiconductor wafer size from a plastic housing composition, where semiconductor chips are embedded by their rear sides and by their edge sides in the plastic housing composition, and the top sides thereof forming the coplanar area with the plastic housing composition without the plastic housing composition or the coplanar area being supported by a circuit substrate. During the injection molding of a panel of this type, the material in the region of the underside of the panel shrinks to a greater extent than the material on the top side of the panel, especially as a plurality of semiconductor chips are arranged in rows and columns. This may lead to an extreme warping after the injection molding since the shrinkage process during cooling is more greatly pronounced in the lower region of the panel than in the upper region of the panel.
Even if corresponding shaping of the injection mold nevertheless succeeds in compensating for this shrinkage effect and provides a panel which, after injection molding, has a warping that is within tolerance, the risk of warping still exists for a panel of this type (i.e., including plastic housing composition and semiconductor chips without any support by a substrate) as soon as the panel is heated to relatively high temperatures. This is because the coefficient of thermal expansion in the lower region of the panel (which consists exclusively of plastic housing composition) is significantly greater than the coefficient of thermal expansion that results from the combination of semiconductor chips and plastic housing composition in that region of such a panel which is near to the top side. This means that the panel that initially appears planar is warped during the further processing processes in which, by way of example, soldering temperatures of up to 260° C. occur, as soon as solder balls are soldered as external contacts onto the coplanar area after the application of a wiring structure.
A degree of warping can occur due to the different coefficients of thermal expansion between underside and top side of the panel so that a panel taken from the soldering furnace is so deformed and warped that it can no longer be separated into individual semiconductor components by the normal means. It is also the case for application of a rewiring structure to a coplanar surface of such a panel that narrow tolerances for a still permissible minimum warping are predefined for the photolithographic processes. Since the photoresist processes with heating methods for the crosslinking of the photoresist also work at up to 160° C., high levels of panel warping cannot be afforded tolerance.
The various known design measures for reducing warping are also unable to solve the problem, particularly of a panel which includes essentially plastic housing composition and semiconductor chips, such as, for example, the “balanced design” described in U.S. Pat. No. 6,331,448 which relates to flat conductor leadframes encapsulated by injection molding. The “balanced design” for metal layers on circuit boards, which is also described in U.S. Pat. No. 6,534,852, cannot be used for solving these problems. Further design measures, such as the types described in U.S. Pat. No. 6,724,080 (in which a heat distribution part is introduced into a position of the plastic housing in order to avoid warping by applying a counterforce against a warping) are unsuitable for the panel at issue here.
Designs with film substrates, such as the types described in U.S. Pat. No. 6,486,002, also cannot be used for solving the problem outlined above. The same applies for the plate-type part with a small coefficient of linear expansion on the semiconductor chip, such as the types described in U.S. Pat. No. 6,225,703.
In addition to design measures, after treatment measures have also been developed for reducing the warping by cooling a panel in the clamped-in planar state or by clamping in a curved system between two planar or plane plates in order to avoid warping of the product after injection molding and in order to prevent defects by clamping part in flat between a lower heating block and an upper heating block, as described in Japanese Patent Document No. JP 608 49 88.